VL001 An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator VL002 Toward Multi-Gigabit Wireless: Design of High-Throughput MIMO Detectors With Hardware-Efficient Architecture VL003 Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for Memory-Dominated Wireless Communication Systems VL004 Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for Memory-Dominated Wireless Communication Systems VL005 Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path VL006 Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration VL007 Interleaving Test Algorithm for Subthreshold Leakage-Current Defects in DRAM Considering the Equal Bit Line Stress VL008 Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path VL009 A Fine-Grain Dynamically Recon?gurable Architecture Aimed at Reducing the FPGA-ASIC Gaps VL010 Area-Efficient Asynchronous Multilevel Single-Track Pipeline Template VL011 Area-Delay Efficient Binary Address in QCA VL012 Parallel AES Encryption Engines for Many-Core Processor Arrays VL013 Low-Complexity Multiplier for GF(2m) Based on All-One Polynomials VL014 Split Radix Algorithm for Length 6th DFT VL015 A Novel modulo Adder for 2n-2k-1 Residue Number System VL016 Low-Power VL017 CORDIC Based Fast Radix-2 DCT Algorithm VL018 Low Latency Systolic Montgomery Multiplier for Finite Field GF (2m) Based on Pentanomials VL019 Design of Digit-Serial FIR Filters: Algorithms VL020 Reduced-Complexity LCC Reed- Solomon Decoder Based on Unified Syndrome Computation VL021 Design of Testable Reversible Sequential Circuits VL022 Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes VL023 Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits VL024 Improvement of the Security of Zigbee by a New Chaotic Algorithm VL025 High-Throughput Multi standard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic VL026 Multicarrier Systems Based on Multistage Layered IFFT Structure Read More >>
